(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming a silicon nitride, L-shaped, sidewall spacer in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Sidewall spacers are used in semiconductor manufacturing. These spacers protect underlying features during processing steps. In particular, silicon nitride sidewall spacers adjacent to transistor gate electrodes are used as masks to protect underlying source and drain regions during doping or implanting steps. As the physical geometry of semiconductor devices shrinks, the spacing between the gate electrodes becomes smaller and smaller.
Referring now to FIG. 1, a cross-section of a partially completed prior art integrated circuit device is shown. A semiconductor substrate 10 is shown. Two transistor gate electrodes 22 are formed overlying the semiconductor substrate 10. The transistor gate electrodes 22 comprise a polysilicon gate layer 18 overlying a gate oxide layer 14. A liner oxide layer 26 is deposited or grown overlying the transistor gate electrodes 22 and the semiconductor substrate 10. A silicon nitride layer 30 is deposited overlying the liner oxide layer 26.
Referring now to FIG. 2, a conventional silicon nitride spacer etch is performed. Sidewall spacers are formed by this etching step. Note the profile 34 or shape of the spacers. The spacer width at the top is only slightly less than the spacer width at the bottom. Where adjacent transistor gates are very narrowly spaced, it may be difficult to fill the gap between these spacers with a dielectric layer. The nearly vertical profile of the spacers may cause voids to form in the dielectric material if the transistor gates are too narrowly spaced.
Referring to FIG. 3, a second prior art example is shown. A semiconductor substrate 40 is provided. Two transistor gate electrodes 52 are formed overlying the semiconductor substrate 40. The transistor gate electrodes 52 comprise a polysilicon gate layer 48 overlying a gate oxide layer 44. A liner oxide layer 56 is deposited overlying the transistor gate electrodes 52 and the semiconductor substrate 40. A silicon nitride layer 60 is deposited overlying the liner oxide layer 56. A second silicon dioxide layer 64 is deposited overlying the silicon nitride layer 60.
Referring now to FIG. 4, a two-layer spacer etch is performed on the device. The second silicon dioxide layer 64 is anisotropically etched to create a rounded spacer profile 68. Here, we see how it is easier to achieve good spacer profiles when using silicon dioxide rather than silicon nitride. The silicon nitride layer 60 is etched through to separate spacers.
Referring now to FIG. 5, a post-etch wet chemical clean is performed. Here, the disadvantage of the additional silicon dioxide layer is apparent. The wet chemical clean removes a portion of the second silicon dioxide layer 64. The resulting profile 64 is shown. This two layer spacer process has four significant problems. First, two layers must be deposited and the total thickness of the two layers limits the spacing of the transistor gates. Second, the spacer etch is more complicated because two different materials must be etched. Third, the final shape of the spacers depends on post-etch chemical cleans. This is especially true if hydrofluoric acid (HF) is used in the post-etch clean. Fourth, the addition of the second silicon dioxide layer adds to the thermal budget of the process. This is significant because this layer would be added following the implantation of the lightly-doped drain regions of the transistors. The additional thermal cycle can change device performance.
Several prior art approaches disclose methods to form and fabricate sidewall spacers. U.S. Pat. No. 5,728,596 to Prall teaches the formation of a spacer layer that is used in forming buried contacts. U.S. Pat. No. 5,858,865 to Juengling et al discloses a spacer etch to facet the corners of the silicon nitride. This is used in the formation of contact plugs. U.S. Pat. No. 5,605,864 to Prall teaches a process to form a removable spacer that is used to improve the buried contact process. Co-pending U.S. patent application Ser. No. 09/439,368 (CS-99-063) to Y. Pradeep et al filed on Nov. 15, 1999 teaches a method of using oxidized silicon overlying nitride to form L-shaped spacers.